Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing
Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing
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DOI：
10.1109/reconfig48160.2019.8994799
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发表时间：
2019-12
期刊：
影响因子：
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通讯作者：
Adrian Tatulian;Soheil Salehi;R. Demara
中科院分区：
文献类型：
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作者：
Adrian Tatulian;Soheil Salehi;R. Demara
近年来，用于信号重构的正交匹配追踪(OMP)算法的硬件实现受到了广泛的关注。在文献中已经提出了一些仅用于cmos的方法，它们通过利用OMP技术中的并行性来最小化开销对吞吐量的影响。在这里，提出了一种使用混合自旋-CMOS硬件的方法，作为利用自旋电子器件和MOS组件的调色板的可重构逻辑结构。最终的交换矩阵利用切片组织的模拟模块，提供放大器、晶体管、电容器和低/高势垒磁隧道结(MTJ)，这些器件可配置为在模拟中实现OMP所需的平方和平方根运算。数字功能块包括6输入可分解查找表和基于自旋的模数转换器，以实现OMP所需的矩阵求逆。这些功能块可通过可编程互连连接到非易失性交叉开关，以减少面积来执行低能量向量矩阵乘法。仿真结果表明，与仅使用CMOS的方法相比，功耗降低了5倍，面积需求减少了26倍。
Recently, significant attention has been given to hardware realization of Orthogonal Matching Pursuit (OMP) algorithms for signal reconstruction. Some CMOS-only approaches have been proposed in the literature which minimize overheads impacting throughput by exploiting parallelism within OMP techniques. Herein, an approach using hybrid spin-CMOS hardware is presented as a reconfigurable logic fabric utilizing a palette of spintronic and MOS components. The resulting fabric utilizes slice-organized analog blocks providing amplifiers, transistors, capacitors, and low-/high-barrier Magnetic Tunnel Junctions (MTJs) which are configurable to realize OMP's required squaring and square-root operations in analog. Digital functional blocks include 6-input fracturable look up tables, and a spin-based analog-to-digital converter to realize matrix inversion needed by OMP. These functional blocks are connectable via programmable interconnect to a non-volatile crossbar to perform low energy vector-matrix multiplication with reduced area. Simulation results indicate a 5-fold reduction in energy consumption and a 26-fold decrease in area requirement compared to CMOS-only approaches.