Functional modeling of RSFQ circuits using Verilog HDL
Functional modeling of RSFQ circuits using Verilog HDL
复制标题
使用 Verilog HDL 对 RSFQ 电路进行功能建模
DOI：
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发表时间：
1997
影响因子：
1.8
通讯作者：
M. Feldman
中科院分区：
文献类型：
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作者：
K. Gaj;Chin;E. Friedman;M. Feldman
电路级仿真速度太慢，不能用于大型RSFQ电路的功能和时序验证。从半导体数字电路设计中已知的另一种方法是在逻辑(门)而不是电路(晶体管或结)级进行模拟。使用诸如Verilog的硬件描述语言(HDL语言)，可以编写每个RSFQ基本门的功能模型。然后，可以使用标准的半导体工业CAD工具来模拟由数百个门和数千个约瑟夫森结组成的大型RSFQ电路。我们已经为超过15个基本的RSFQ门开发了Verilog模型库。我们详细描述了我们的DRO RSFQ单元的模型。我们展示了如何将该模型推广到其他更复杂的细胞。我们的库已经在三个大型RSFQ电路的时序设计中得到了验证。
Circuit level simulation is too slow to be used for verification of function and timing of large RSFQ circuits. The alternative, known from semiconductor digital circuit design, is simulating at the logic (gate) instead of the circuit (transistor or junction) level. Using a hardware description language (HDL) such as Verilog, it is possible to write functional model of each of the RSFQ basic gates. A large RSFQ circuit composed of hundreds gates and thousands Josephson junctions can then be simulated using standard semiconductor industry CAD tools. We have developed a library of Verilog models for over 15 basic RSFQ gates. We describe in detail our model for the DRO RSFQ cell. We show how this model can be generalized for other more complex cells. Our library has been verified by employing it in the design of timing for three large RSFQ circuits.