The Design of an SRAM-BasedField-Programmable Gate Array , Part I :
The Design of an SRAM-BasedField-Programmable Gate Array , Part I :
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基于 SRAM 的现场可编程门阵列的设计，第一部分：
DOI：
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
K. Chung
中科院分区：
文献类型：
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作者：
ArchitecturePaul;Chow;Soon Ong Seo;Jonathan Rose;K. Chung
|现场可编程门阵列 (FPGA) 现在广泛用于数字系统的实现，并且有许多商业架构可供使用。尽管文献和数据手册包含这些架构的详细描述，但关于如何选择高级架构的信息很少，也没有关于器件的电路级或物理设计的信息。本文第一部分描述了 SRAM 可编程 FPGA 的高级架构设计。第二部分将解决电路设计问题直至物理布局。 FPGA 的逻辑块和布线架构是通过基准电路和定制 CAD 工具进行实验确定的。由此产生的逻辑块是硬连线在一起的四输入查找表的不对称树，以及具有精心选择的段长度分布的分段路由架构。
| Field-Programmable Gate Arrays (FPGAs) are now widely used for the implementation of digital systems and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. This paper, Part I, describes the high-level architectural design of an SRAM-programmable FPGA. Part II will address the circuit design issues through to the physical layout. The logic block and routing architecture of the FPGA was determined through experimentation with benchmark circuits and custom-built CAD tools. The resulting logic block is an asymmetric tree of four-input lookup tables that are hard-wired together and a segmented routing architecture with a carefully chosen segment length distribution.