Statistical Design Framework of Submicron Flip-Flop Circuits Considering Process Variations
Statistical Design Framework of Submicron Flip-Flop Circuits Considering Process Variations
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DOI：
10.1109/tsm.2010.2080693
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发表时间：
2011-02
影响因子：
2.7
通讯作者：
Sayed Alireza Sadrossadat;Hassan Mostafa;M. Anis
中科院分区：
文献类型：
--
作者：
Sayed Alireza Sadrossadat;Hassan Mostafa;M. Anis
本文提出了一种触发器电路统计设计框架，以实现高产率，同时满足性能、泄漏功率、开关功率和布局面积设计规范。所提出的设计方案提供了标称设计参数，即，触发器晶体管的宽度和长度，其提供对晶体管尺寸和阈值电压的工艺变化的最大抗扰性。所提出的框架表明，对于一个给定的触发器设计规格，可以实现一定的产量。为了进一步提高这一收益率，建议的框架显示，设计规范应该放宽。基于传输门的主从触发器被选为本文的设计案例研究，然而，所提出的框架适用于任何其他触发器电路在纳米政权。
In this paper, a framework for the statistical design of the flip-flops circuits is proposed to achieve a high yield, while meeting the performance, leakage power, switching power, and layout area design specifications. The proposed design solution provides the nominal design parameters, i.e., the widths and lengths of the flip-flop transistors, which provide maximum immunity to the process variations in the transistor dimensions and threshold voltage. The proposed framework shows that for a given flip-flop design specifications, a certain yield can be achieved. To further increase this yield, the proposed framework shows which design specifications should be relaxed. The transmission gate-based master-slave flip-flop is selected as a design case study in this paper, however, the proposed framework is applicable to any other flip-flop circuit in the nanometer regime.