High-Q capacitors implemented in a CMOS process for low-power wireless applications
High-Q capacitors implemented in a CMOS process for low-power wireless applications
复制标题
DOI：
10.1109/22.668648
复制
发表时间：
1998-05
影响因子：
4.3
通讯作者：
C. Hung;Y. Ho;I. Wu
中科院分区：
文献类型：
--
作者：
C. Hung;Y. Ho;I. Wu
在一个代工0.8-/spl mu/m CMOS工艺，低成本的电容器与测量的Q值约为50，在3 GHz和高本征电容/面积（/spl sim/200 nF/cm/sup 2/）被证明。当外推到900 MHz时，Q因子大于100。电容器采用多晶硅到n阱MOS结构，由于n阱薄层电阻高（/spl sim/1 k/spl Omega/spl square/），该结构通常不适用于高Q应用。利用该结构，实现了谐振频率为960 MHz、功率增益为16.2 dB、1 dB压缩点（P/sub 1 dB/）为-5 dBm、噪声系数为3.5 dB的低噪声放大器（LNA）。使用经验法则，根据P/sub 1 dB/数据，三阶谐波截距点（P/sub IP 3/）估计为5 dBm。尽管对电容器的非线性的关注，这些结果表明，这种电容器结构可以用于LNA的具有大的动态范围。
In a foundry 0.8-/spl mu/m CMOS process, low-cost capacitors with a measured Q factor of around 50 at 3 GHz and high intrinsic capacitance/area (/spl sim/200 nF/cm/sup 2/) were demonstrated. When extrapolated to 900 MHz, the Q factor is greater than 100. The capacitors use a poly-to-n-well MOS structure which has been commonly dismissed for high-Q applications due to the high n-well sheet resistance (/spl sim/1 k/spl Omega///spl square/). Utilizing the structure, a low-noise amplifier (LNA) with a resonant frequency of 960 MHz, power gain of 16.2 dB, 1-dB compression point (P/sub 1 dB/) of -5 dBm, and noise figure of 3.5 dB was demonstrated. Using a rule of thumb, the third-order harmonic intercept point (P/sub IP3/) was estimated to be 5 dBm from the P/sub 1 dB/ data. Despite concerns for nonlinearity of the capacitors, these results suggest that this capacitor structure could be used in LNA's with a large dynamic range.