A review of yield modelling techniques for semiconductor manufacturing
A review of yield modelling techniques for semiconductor manufacturing
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DOI：
10.1080/00207540600596874
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发表时间：
2006-12
影响因子：
9.2
通讯作者：
Naveen Kumar;Kathryn Kennedy;K. Gildersleeve;Richard Abelson;Christina M. Mastrangelo;Douglas C. Montgomery
中科院分区：
文献类型：
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作者：
Naveen Kumar;Kathryn Kennedy;K. Gildersleeve;Richard Abelson;Christina M. Mastrangelo;Douglas C. Montgomery
半导体制造是一个复杂的多级制造过程，晶圆厂使用复杂的工艺，涉及价值数十亿美元的设备来生产集成电路。与集成电路相关的复杂性水平在特征尺寸和器件数量方面正在增加。公司使用缺陷率、产量和周期时间等多种绩效指标来提高制造绩效。通过可靠、准确的质量控制措施保持高产量是公司采用的关键绩效标准之一。本文的目的是对涉及产量建模关键方面的文献进行回顾。将提供对许多主题的回顾，从简单的概率良率模型到空间缺陷和径向良率损失等关键特征的结合。我们还将评估用于对与复杂的相互关联的晶圆制造工艺相关的变化进行建模的经验技术。我们强调，不应孤立地考虑良率建模，集成良率建模和分析需要系统范围的方面。
Semiconductor manufacturing is a complex multistage manufacturing process, and wafer fabs use complex processes involving billions of dollars worth of equipment to produce integrated circuits. The level of complexities associated with an integrated circuit is increasing in terms of feature size and number of devices. Companies use several performance metrics such as defectiveness, yield, and cycle time to improve manufacturing performance. Maintaining high yield through reliable and accurate quality control measures is one of the key performance criteria used by companies. The intent of this paper is to provide a review of the literature dealing with critical aspects of yield modelling. A review of many topics from simple probabilistic yield models to the incorporation of critical features such as spatial defects and radial yield losses will be provided. We will also assess empirical techniques used to model variations associated with complex interrelated wafer manufacturing processes. We emphasize that yield modelling should not be considered in isolation and system-wide aspects are necessary for integrated yield modelling and analysis.