Hardware architecture for list successive cancellation polar decoder
Hardware architecture for list successive cancellation polar decoder
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DOI：
10.1109/iscas.2014.6865102
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发表时间：
2014-06
期刊：
影响因子：
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通讯作者：
Chuan Zhang;X. You;Jin Sha
中科院分区：
文献类型：
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作者：
Chuan Zhang;X. You;Jin Sha
本文旨在设计一个有效的硬件架构，以成功取消（SC）Polar解码器，与传统的SC解码器相比，List SC解码器可以接近最大可能性（ML）解码器的性能，尚未提出有效的SC解码器来解决此问题列表尺寸L的选择是通过引入前计算技术来评估的与传统设计方法相比，提议的解码器可以以更少的硬件成本和延迟来实现近乎最佳的解码性能。列表SC极地解码器的应用。
This paper aims at designing an efficient hardware architecture for list successive cancellation (SC) polar decoder. Previous literatures have shown that, compared to conventional SC decoder, list SC decoder has the ability to approach the performance of maximum likelihood (ML) decoder. However, the efficient implementation of list SC decoder has not been proposed yet. To tackle this issue, first we propose a sub-optimal version of list SC decoding. Then different selections of list size L are evaluated. By introducing the pre-computation technique, the hardware architecture for a list SC decoder with L = 2 is proposed. Comparison results have shown that, for a rate-½ (1024, 512) polar code, the proposed decoder can achieve near-optimal decoding performance with less hardware cost and latency than the decoder with conventional design approach. We believe that the design approach presented in this paper will facilitate practical applications of list SC polar decoder.