Utilizing Assertion Synthesis to Achieve an Automated Assertion-Based Verification Methodology for Complex Graphics Chip Designs
Utilizing Assertion Synthesis to Achieve an Automated Assertion-Based Verification Methodology for Complex Graphics Chip Designs
复制标题
利用断言合成实现复杂图形芯片设计的基于断言的自动验证方法
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
Peter Nelson
中科院分区：
文献类型：
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作者：
Prosenjit Chatterjee;Yuan Lu;Saad Godil;Peter Nelson
本文提出了一种新的功能验证方法，使用断言合成自动生成断言和功能覆盖目标。这种新的方法补充和增强我们现有的验证流程的基础上约束随机模拟，正式验证以及仿真。我们的实验结果支持新的方法提供。
This paper reports a new functional verification methodology using assertion synthesis to automatically generate assertions and functional coverage goals. This new methodology complements and enhances our existing verification flows based on constrained random simulation, formal verification as well as emulation. Our experimental results supporting the new methodology are provided.