An Easily Testable Routing Architecture and Prototype Chip
An Easily Testable Routing Architecture and Prototype Chip
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易于测试的路由架构和原型芯片
DOI：
10.1587/transinf.e95.d.303
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
T. Sueyoshi
中科院分区：
文献类型：
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作者：
Kazuki Inoue;Masahiro Koga;Motoki Amagasaki;M. Iida;Yoshinobu Ichida;Mitsuro Saji;J. Iida;T. Sueyoshi
通常，与ASIC相比，诸如FPGA的可编程LSI难以测试。这主要有两个原因。首先是由于FPGA的可编程性，不能使用自动测试模式生成器（ATPG）。另一个原因是FPGA架构非常复杂。在本文中，我们提出了一种新的FPGA架构，将简化设备的测试。我们的架构是基于一般的岛式FPGA架构，但它由几种类型的电路块和有序的线连接。本文还提出了有效的测试配置，我们提出的架构。我们使用原型芯片评估了我们的架构和测试配置。因此，使用我们的配置在很短的测试时间内对芯片进行了全面测试。此外，我们的架构可以提供与传统的FPGA架构相当的性能。
Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture.