A 4.2 ps Time-Interval RMS Resolution Time-to-Digital Converter Using a Bin Decimation Method in an UltraScale FPGA
A 4.2 ps Time-Interval RMS Resolution Time-to-Digital Converter Using a Bin Decimation Method in an UltraScale FPGA
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DOI：
10.1109/tns.2016.2606627
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发表时间：
2016-09
影响因子：
1.8
通讯作者：
Yonggang Wang;Chong Liu
中科院分区：
文献类型：
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作者：
Yonggang Wang;Chong Liu
基于现场可编程门阵列 (FPGA) 的时间数字转换器 (TDC) 的常见解决方案是构建用于时间插值的抽头延迟线 (TDL)，以产生子时钟时间分辨率。 TDL延迟元素的粒度和均匀性决定了TDC时间分辨率。在本文中，我们提出了一种双采样 TDL 架构和一种 bin 抽取方法，可以使延迟元素尽可能小且均匀，从而使实现的 TDC 能够实现超出固有单元延迟的高时间分辨率。在 Xilinx UltraScale FPGA 中实现了两个相同的完全基于硬件的 TDC，以进行性能评估。对于0到440 ns范围内的固定时间间隔，由两个TDC测量的平均时间间隔RMS分辨率为4.2 ps，因此得出单个TDC的时间戳分辨率为2.97 ps。 TDC 的最大命中率高达 FPGA 系统时钟频率的一半，即我们的演示原型中的 250 MHz。由于不需要传统的在线逐箱校准，因此所提出的 TDC 的实施非常简单并且相对节省资源。
The common solution for a field programmable gate array (FPGA)-based time-to-digital converter (TDC) is constructing a tapped delay line (TDL) for time interpolation to yield a sub-clock time resolution. The granularity and uniformity of the delay elements of TDL determine the TDC time resolution. In this paper, we propose a dual-sampling TDL architecture and a bin decimation method that could make the delay elements as small and uniform as possible, so that the implemented TDCs can achieve a high time resolution beyond the intrinsic cell delay. Two identical full hardware-based TDCs were implemented in a Xilinx UltraScale FPGA for performance evaluation. For fixed time intervals in the range from 0 to 440 ns, the average time-interval RMS resolution is measured by the two TDCs with 4.2 ps, thus the timestamp resolution of single TDC is derived as 2.97 ps. The maximum hit rate of the TDC is as high as half the system clock rate of FPGA, namely 250 MHz in our demo prototype. Because the conventional online bin-by-bin calibration is not needed, the implementation of the proposed TDC is straightforward and relatively resource-saving.