Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure
Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure
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发表时间：
2006-06
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通讯作者：
S. Suk;Ming Li;Y. Yeoh;K. Yeo;J. K. Ha;Hyunseok Lim;Hyunwoo Park;Dong-Won Kim;T. Chung;K. Oh;Wonshik Lee
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作者：
S. Suk;Ming Li;Y. Yeoh;K. Yeo;J. K. Ha;Hyunseok Lim;Hyunwoo Park;Dong-Won Kim;T. Chung;K. Oh;Wonshik Lee
采用传统工艺在SOI结构中成功研制出亚5 nm三栅纳米线MOSFET，具有良好的均匀性。多晶硅沟道的性能进行了比较，与单硅沟道。在LG ~ 5 nm处，由于弹道效率的提高，n-FET的通态电流在单硅沟道达到802 μ A/um，而在多晶硅沟道达到471 μ A/um，是单硅沟道的60%。在非常小的LG约5纳米，我们还调查了关漏电流与升压BJT操作。
Sub 5 nm tri-gate nanowire MOSFET is successfully developed with good uniformity by using conventional technology in the SOI structure. Performance of the poly Si channel is compared with that of the single Si channel. On-state current of n-FET has attained to 802 uA/um for single Si channel, while 471 uA/um for poly Si channel, which is 60 % of performance of the single Si channel at LG ~ 5 nm due to the enhancement of ballistic efficiency. At the extremely small LG of around 5 nm, we also investigate off-leakage current with boosted BJT operation.