Multiplier energy reduction through bypassing of partial products
Multiplier energy reduction through bypassing of partial products
复制标题
通过绕过部分乘积来减少乘法器能量
DOI：
10.1109/apccas.2002.1115097
复制
发表时间：
2002
期刊：
影响因子：
--
通讯作者：
Koji Inoue
中科院分区：
文献类型：
--
作者：
Jun;V. Moshnyaga;Koji Inoue
便携式电池供电的多媒体设备的设计需要节能的乘法电路。提出了一种基于部分积动态旁路的数字乘法器低功耗设计方法。乘法器硬件中的旁路元件消除了当部分积为零时进位保留加法器中出现的冗余信号转换。对实际DCT数据的仿真结果表明，该方法可使相关方法的功耗节省12%，与它们联合使用时，可使16/spl times/16数字CMOS乘法器的功耗降低31%，面积开销降低25%，最坏情况下性能下降小于4%.电路实现概述。
The design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital multiplier based on dynamic bypassing of partial products. The bypassing elements incorporated into the multiplier hardware eliminate redundant signal transitions, which appear within the carry-save adders when the partial product is zero. Simulations on the real-life DCT data show that the proposed approach can improve power saving of related methods by 12%, while jointly with them, it reduces the power consumption of a 16/spl times/16 digital CMOS multiplier by 31%, with 25% area overhead and less than 4% performance degradation in the worst case. The circuit implementation is outlined.