Branch-directed and stride-based data cache prefetching
Branch-directed and stride-based data cache prefetching
复制标题
分支导向和基于步幅的数据缓存预取
DOI：
10.1109/iccd.1996.563561
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发表时间：
1996
期刊：
影响因子：
--
通讯作者：
D. Kaeli
中科院分区：
文献类型：
--
作者：
Yue Liu;D. Kaeli
高速缓冲存储器通常用于减小微处理器和存储器技术之间的性能差距。为了增加高速缓存在被请求时可以提供指令和数据的机会，可以采用预取。预取尝试用将在不久的将来被访问的指令和数据来准备该高速缓存。提出的工作描述了一种预取算法，该算法将数据缓存预取绑定到指令流中的分支。数据引用的历史被合并到分支目标缓冲区（BTB）中。由于分支指令决定遵循哪个指令路径，因此数据访问模式也取决于分支行为。实验结果表明，将该策略与标记预取相结合，可以显著提高缓存命中率。虽然提高缓存命中率是很重要的，我们的预取策略显着减少了整体内存总线流量。
Cache memories are commonly used to reduce the performance gap between microprocessor and memory technology. To increase the chances that a cache can provide instructions and data when requested, prefetching can be employed. Prefetching attempts to prime the cache with instructions and data which will be accessed in the near future. The work presented describes a prefetching algorithm which ties data cache prefetching to branches in the instruction stream. History of the data references is incorporated into a branch target buffer (BTB). Since branch instructions determine which instruction path is followed data access patterns are also dependent upon branch behavior. Results indicate that combining this strategy with tagged prefetching can significantly improve cache hit ratios. While improving cache hit rates is important, our prefetching policy significantly reduces the overall memory bus traffic.