A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing
A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing
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DOI：
10.1109/jssc.2010.2048139
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发表时间：
2010-07
影响因子：
5.4
通讯作者：
Jing Yang;T. Naing;R. Brodersen
中科院分区：
文献类型：
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作者：
Jing Yang;T. Naing;R. Brodersen
基于二进制逐次逼近（SA）算法，采用串联电容梯形将两个ADC时间交错，实现了异步6位1 GS/s ADC。半闭环异步技术消除了内部时钟过高的问题，大大提高了SA算法的速度。在这种设计中，降低功耗的一个关键特性是使用纠错技术放宽比较器的要求，这可以看作是SA算法的扩展，以消除由于亚稳态而导致的退化。该器件采用65 nm CMOS工艺，有源面积为0.11 mm2，在1GS/s采样率下峰值SNDR为31.5 dB，总功耗为6.7 mW。
An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on the binary successive approximation (SA) algorithm using a series capacitive ladder. The semi-closed loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. A key feature to reduce the power in this design involves relaxing the comparator requirements using an error correction technique, which can be viewed as an extension of the SA algorithm to remove degradation due to metastability. Fabricated in 65 nm CMOS with an active area of 0.11 mm2, it achieves a peak SNDR of 31.5 dB at 1GS/s sampling rate and has a total power consumption of 6.7 mW.