ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
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DOI：
10.1145/1735023.1735058
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发表时间：
2010-03
期刊：
影响因子：
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通讯作者：
C. Sze
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作者：
C. Sze
在演讲中，我们将详细介绍ISPD 2010高性能时钟网络综合竞赛的具体内容。与2009年的第一届时钟网络合成大赛相比，规则进行了修改，以更好地反映行业的真实的问题。在两次不同电源电压设置的仿真中，总时钟功率（由电容建模）被设置为主要判断标准，而不是时钟延迟范围。然而，有效的时钟分配网络解决方案必须具有在预设限制下的本地时钟偏斜。将仅实施局部时钟偏斜约束，因为（1）早期模式时序违规通常限于局部区域中，以及（2）局部时序违规通常直接导致非常难以修复的拥塞问题。此外，延迟变化将在比赛中制定和简化的蒙特卡罗模拟将用于评估有效的解决方案。更重要的是，一套新的基准将被宣布，并用于决定比赛的赢家。这些测试用例都是直接来自真实的工业微处理器和高性能ASIC设计，它们有超过1000个时钟接收器。十多个学术时钟合成工具参加了比赛，最终结果将在本次演讲中公布。
In the talk, the details of ISPD 2010 high performance clock network synthesis contest will be introduced. Compared to first clock network synthesis contest in 2009, the rules have been revised to better reflect the real problems from the industry. Instead of clock latency range upon two simulations with different supply voltage settings, the total clock power (modeled by capacitance) is set to be the major judging criteria. However, a valid clock distribution network solution must have local clock skew under a preset limit. Only local clock skew constraints will be enforced because (1) early mode timing violations are often limited in local regions, and (2) local timing violations often directly lead to congestion problems which are very hard to fix. Moreover, delay variation will be formulated in the contest and simplified Monte Carlo simulation will be used to evaluate valid solutions. More importantly, a new set of benchmarks will be announced and used to decide the winner of the contest. These test-cases are all directly derived from real industrial microprocessor and high-performance ASIC designs and they have over 1000 clock sinks. More than ten academic clock synthesis tools have participated in the contest and the final results will be announced during this talk.