CACTI: An enhanced cache access and cycle time model
CACTI: An enhanced cache access and cycle time model
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DOI：
10.1109/4.509850
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发表时间：
1996-05-01
影响因子：
5.4
通讯作者：
Jouppi, NP
中科院分区：
文献类型：
--
作者：
Wilton, SJE;Jouppi, NP
本文描述了片上直接映射缓存和集合关联缓存的访问和周期时间的分析模型。模型的输入是缓存大小、块大小和关联性，以及数组组织和进程参数。对于我们所选择的电路，该模型给出的估计在Hspice结果的6%以内。这个模型扩展了以前的模型，并修复了它们的许多主要缺点。新特性包括标签阵列、比较器和多路复用驱动器的模型、无阶跃输入斜坡、存储器子阵列的矩形堆叠、晶体管级解码器模型、由附加阵列组织参数控制的列多路位线、用于字线驱动器的负载相关晶体管尺寸、周期时间和访问时间的输出。实现该模型的软件可通过ftp获得。
This paper describes an analytical model for the access and cycle times of on-chip direct-mapped and set-associative caches. The inputs to the model are the cache size, block size, and associativity, as well as array organization and process parameters. The model gives estimates that are within 6% of Hspice results for the circuits we have chosen.This model extends previous models and fixes many of their major shortcomings. New features include models for the tag array, comparator, and multiplexor drivers, nonstep stage input slopes, rectangular stacking of memory subarrays, a transistor-level decoder model, column-multiplexed bitlines controlled by an additional array organizational parameter, load-dependent size transistors for wordline drivers, and output of cycle times as well as access times.Software implementing the model is available via ftp.