SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation

SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation
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DOI:
10.1109/cicc.2012.6330636
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发表时间:
2012-10
期刊:
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference
影响因子:
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通讯作者:
E. Painkras;L. Plana;J. Garside;S. Temple;Simon Davidson;J. Pepper;David M. Clark;Cameron Patterson;S. Furber
E. Painkras;L. Plana;J. Garside;S. Temple;Simon Davidson;J. Pepper;David M. Clark;Cameron Patterson;S. Furber
中科院分区:
其他
文献类型:
--
作者:
E. Painkras;L. Plana;J. Garside;S. Temple;Simon Davidson;J. Pepper;David M. Clark;Cameron Patterson;S. Furber

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The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements.