Scaling up of wave pipelines
Scaling up of wave pipelines
复制标题
扩大波浪管道
DOI：
10.1109/icvd.2001.902697
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
Tadao Nakamura
中科院分区：
文献类型：
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作者：
M. Fukase;Ryusuke Egawa;Tomoaki Sato;Tadao Nakamura
波流水线是一种基于延迟平衡以流水线方式布置同步逻辑电路的技术，其允许比公知的常规流水线更高的时钟速率。为了适应集成电路集成度越来越高的发展趋势，提高波形流水线电路的规模，本文首先研究了结构简单的波形流水线电路的规模相关特性。结果表明，更大的规模是更有利的流水线程度和向量执行时间。其次，我们探索了具有相当规模和复杂结构的多功能波浪管道。从软件开销和面积两方面考虑，建议多功能电路采用全波流水结构。第三，我们展示了一个全波流水标量处理单元的标准单元综合，以证明波流水多功能随机逻辑电路的实用性。采用0.5-/spl μ/m CMOS工艺，在2.3-mm/spl times/2.3-mm芯片上实现了标量处理单元，电路级仿真估计其时钟速度为1GHz。
Wave pipelining is a technique of arranging synchronous logic circuits in a pipeline fashion based on delay balancing that allows clocking rate higher than that of well-known regular pipelining. In order to scale up wave-pipelined circuits in the trend of VLSI development toward tighter integration, firstly we investigate scale-dependent characteristics of those circuits with simple structure. It is shown that larger scale is more favorable in view of pipeline degree and vector-execution time. Secondly we explore multifunctional wave pipelines with considerable scales and complicated structures. A fully wave-pipelined structure is recommended to multifunctional circuits regarding software overheads and areas. Thirdly, we show the standard cell synthesis of a fully wave-pipelined scalar processing unit to demonstrate the practicality of wave pipelining multifunctional random logic circuits. By using 0.5-/spl mu/m CMOS technology, a scalar processing unit is implemented in a 2.3-mm/spl times/2.3-mm chip whose clock speed is estimated to be 1 GHz from circuit level simulation.