A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches
A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches
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DOI：
10.1109/tim.2003.822717
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发表时间：
2004-04
影响因子：
5.6
通讯作者：
Masaru Fukushi;S. Horiguchi
中科院分区：
文献类型：
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作者：
Masaru Fukushi;S. Horiguchi
本文讨论了在存在故障处理器的情况下重新配置网状连接的处理器阵列(网状阵列)的问题。对于大规模并行系统，有必要开发能够自动重新配置部分故障系统的内置自重新配置系统。到目前为止，已经提出了许多重构方法，但大多数方法都不适合自重构。本文提出了一种基于简单列旁路和南向重路的自重构方法。该方案具有重新配置成功率高、硬件开销低、实现简单等优点。切换机制可以利用相邻处理器的状态自动确定所需的切换功能，从而使我们的方法更容易实现。仿真结果表明，在冗余开关和互连数量减半的情况下，该方法获得了比以往方法更高的系统成品率。利用现场可编程门阵列(现场可编程门阵列)实现了自重构网状阵列的原型系统，并讨论了硬件开销。
This paper deals with the issue of reconfiguring mesh-connected processor arrays (mesh arrays) in the presence of faulty processors. For massively parallel systems, it has become necessary to develop built-in self-reconfigurable systems that can automatically reconfigure partially faulty systems. Many reconfiguration methods have been proposed to date; however, most of them are not suitable for self-reconfiguration. In this paper, we propose a self-reconfiguration method based on simple column bypass and south directional rerouting schemes. This proposal offers the combined advantages of high probability of successful reconfiguration, low hardware overhead, and simplicity of implementation. A switching mechanism, which can determine the desired switch functions automatically using the states of neighboring processors, makes the implementation of our method easier. Simulated results show that the proposed method achieves a higher system yield than that of previous methods with half the number of redundant switches and interconnections. The prototype system of self-reconfigurable mesh arrays is implemented using a field-programmable gate array (FPGA) and the hardware overhead is discussed.