High-level Synthesis of ∆ Σ Modulator Topologies Optimized for Complexity , Sensitivity and Power Consumption
High-level Synthesis of ∆ Σ Modulator Topologies Optimized for Complexity , Sensitivity and Power Consumption
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通讯作者：
Hua Tang;A. Doboli
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作者：
Hua Tang;A. Doboli
本文提出了一种新颖的单回路单比特∆Σ调制器拓扑综合方法。目标是探索所有可能的拓扑结构，并在各种设计考虑（如硬件复杂性、调制器灵敏度和功耗）下获得最佳拓扑结构。我们定义了一个通用的调制器架构，它包含了所有可能的反馈和前馈信号路径，并推导了通用拓扑的符号噪声传递函数（NTF）和信号传递函数（STF）。然后，我们使用符号函数将拓扑探索问题表述为MINLP（混合整数非线性约束规划）问题，该问题同时生成并选择相对于成本函数的最优调制器拓扑。实验表明，与传统的调制器拓扑结构相比，合成拓扑结构具有优越性。
This paper proposes a novel topology synthesis methodology for single-loop single-bit ∆Σ modulators. The goal is to explore all possible topologies and obtain the optimal topology under various design considerations, such as hardware complexity, modulator sensitivity and power consumption. We defined a generic modulator architecture that incorporates all possible feedback and feedforward signal paths, and we derived the symbolic Noise Transfer Function (NTF) and Signal Transfer Function (STF) for the generic topology. We then used the symbolic functions to formulate the topology exploration problem as a MINLP (Mixed-Integer Nonlinearly Constrained Programming) problem that simultaneously generates and selects the optimal modulator topology with respect to the cost function. Experiments show the superiority of synthesized topologies as compared to traditional modulator topologies.