A 290 mV Sub-V(T) ASIC for Real-Time Atrial Fibrillation Detection.
A 290 mV Sub-V(T) ASIC for Real-Time Atrial Fibrillation Detection.
复制标题
用于实时心房颤动检测的 290 mV Sub-V(T) ASIC。
DOI：
10.1109/tbcas.2014.2354054
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发表时间：
2015
影响因子：
5.1
通讯作者：
Rodrigues,JoachimNeves
中科院分区：
文献类型：
--
作者：
Andersson,Oskar;Chon,KiH;Sornmo,Leif;Rodrigues,JoachimNeves
心房颤动发作的实时检测器被制作为一个应用专用集成电路（ASIC）。检测的基础是表征RR区间序列的三个参数，即拐点比、连续差的均方根和香农熵。所开发的硬件架构以超低电压运行为目标，适用于具有超低能耗要求的植入式环路记录仪。算法和架构优化，以最大限度地减少面积和能量消耗，总面积占地面积减少44%。该设计采用65纳米CMOS低漏高阈值技术制造。在亚阈值（sub-VT）区域使用积极缩放的电源电压（VDD）进行的测量显示，与标称vdd1.2 V相比，当工作在1 kHz， vdd300 mV时，节能高达41倍。
A real-time detector for episodes of atrial fibrillation is fabricated as an application specific integrated circuit (ASIC). The basis for detection is a set of three parameters for characterizing the RR interval series, i.e., turning point ratio, root mean square of successive differences, and Shannon entropy. The developed hardware architecture targets ultra-low voltage operation, suitable for implantable loop recorders with ultra-low energy requirements. Algorithmic and architectural optimizations are performed to minimize area and energy dissipation, with a total area footprint reduction of 44%. The design is fabricated in 65-nm CMOS low-leakage high-threshold technology. Measurements with aggressively scaled supply voltage (VDD) in the subthreshold (sub-VT) region show energy savings of up to 41 X when operating at 1 kHz with a VDDof 300 mV compared to a nominal VDDof 1.2 V.