System-level yield optimisation using hierarchical-based design flow
System-level yield optimisation using hierarchical-based design flow
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DOI：
10.1049/el.2009.0393
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发表时间：
2009-06
影响因子：
1.1
通讯作者：
S. Ali;P. Wilson;R. Wilcock
中科院分区：
文献类型：
--
作者：
S. Ali;P. Wilson;R. Wilcock
提出了一种新的分层优化方法，能够优化系统级模拟电路设计的性能和产量。开发了一种行为模型，该模型结合了帕累托前沿的性能和变化，可用于优化系统级结构。结果已被验证与晶体管级仿真的PLL和建议，准确的性能和产量预测可以实现与建议的设计方法。
A new approach in hierarchical optimisation is presented, capable of optimising both the performance and yield of a system-level analogue circuit design. A behavioural model that combines the performance and variation from a Pareto-front is developed which can be used to optimise the system-level structure. The results have been verified with transistor-level simulations of a PLL and suggest that accurate performance and yield prediction can be achieved with the proposed design methodology.