Timing Domain Crossing using Muller Pipelines
Timing Domain Crossing using Muller Pipelines
复制标题
使用 Muller 管道进行时域交叉
DOI：
10.1109/async49171.2020.00014
复制
发表时间：
2020
期刊：
影响因子：
--
通讯作者：
A. Steininger
中科院分区：
文献类型：
--
作者：
F. Huemer;A. Steininger
当代系统的复杂性和模块化程度不断提高，加上参数可变性不断增加，使得灵活、稳健且高效的模块级互连变得非常有用。在这种情况下，全局异步本地同步（GALS）系统为经典严格同步互连提供了可行的替代方案。然而，有了这个概念，就需要不同时钟和定时域之间的可靠接口。在本文中，我们提出了一种用于时序域交叉接口的新颖方法，该方法能够安全地将令牌（即零位消息）从同步传输到异步时序域，反之亦然。新方法的核心是使用 Muller 管道，其中读取令牌同步写入和读取。以不丢失任何令牌的方式执行此操作，需要同步定时域具有有关 Muller 管道的填充级别的准确状态信息（即，执行写入或读取操作是否安全）。我们深入分析了如何获取这些状态信息，并提出了一个简单的管道采样模型。此外，我们还讨论了这些概念所依赖的时序约束以及如何处理不可避免地出现在此类接口上的亚稳态。所提出的结构的一种可能用途是同步/异步或双同步 FIFO 的控制路径，我们用它来说明原理并展示实际可行性。
The increasing complexity and modularity of contemporary systems, paired with increasing parameter variabilities, makes the availability of flexible and robust, yet efficient, module-level interconnect instrumental. In this context Globally Asynchronous Locally Synchronous (GALS) systems offer a viable alternative to classical strictly synchronous interconnect. However, with this concept a need for reliable interfaces between different clock and timing domains arises. In this paper we propose a novel approach for timing domain crossing interfaces which are able to safely transfer (read) tokens (i.e., zero-bit messages) from a synchronous into an asynchronous timing domain and vice versa. At its core the new approach uses a Muller pipeline where read tokens are synchronously written to and read from. Doing this in a way that does not lose any tokens, requires the synchronous timing domain to have exact state information about the fill-level of the Muller pipeline (i.e., is it safe to perform a write or read operation). We thoroughly analyze how this state information can be obtained and propose a simple pipeline sampling model. Furthermore we discuss what timing constraints these concepts rely on and how to deal with metastability that inevitably appears at such interfaces. One possible use of the proposed structures is the control path of synchronous/asynchronous or bisynchronous FIFOs, which we use to illustrate the principle and show the practical feasibility.