Selection of an error-correcting code for FPGA-based physical unclonable functions
Selection of an error-correcting code for FPGA-based physical unclonable functions
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为基于 FPGA 的物理不可克隆功能选择纠错码
DOI：
10.1109/fpt.2017.8280151
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
K. Gaj
中科院分区：
文献类型：
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作者：
Brian Jarvis;K. Gaj
本文探讨了具有物理不可克隆函数的模糊提取器应用中的纠错码。我们研究了BCH代码，并使用剩余熵、解码器故障概率和硬件要求的标准将它们与卷积代码进行了比较。对并行BCH编码进行了分析，并进行了全面的搜索，以找到满足并行设计标准的最小BCH代码，以产生128、192和256位密钥。选择卷积代码与本分析中发现的BCH代码进行比较。分析了所选代码在模糊提取器设计中的应用。比较了每种代码的FPGA实现的硬件要求，并针对Artix-7和Spartan-6 FPGA系列实现了BCH解码器设计。我们发现（127,22,47）并行BCH代码或（2,1,12）卷积代码的性能与单个大型BCH代码一样好，同时当可以利用块ram时需要更少的FPGA资源。卷积码还需要最少的PUF ID位。
This paper explores error-correcting codes for fuzzy extractor applications with Physical Unclonable Functions. We investigate BCH codes and compare them to convolutional codes using criteria of remaining entropy, probability of decoder failure, and hardware requirements. Parallel BCH coding is analyzed with a comprehensive search performed to find the smallest BCH code which satisfies the criteria in a parallel design to produce 128, 192, and 256-bit keys. A convolutional code is selected for comparison against the BCH codes found in this analysis. Application of the selected codes to a fuzzy extractor design is analyzed. Hardware requirements for FPGA implementations of each code is compared, with a BCH decoder design implemented for Artix-7 and Spartan-6 FPGA families. We find that a (127, 22, 47) parallel BCH code or (2, 1, 12) convolutional code is capable of performing as well as a single large BCH code, while requiring fewer FPGA resources when block RAMs can be leveraged. The convolutional code additionally requires the least amount of PUF ID bits.