Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems
Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems
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DOI：
10.1145/2906363.2906369
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发表时间：
2016-05
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影响因子：
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通讯作者：
Arno Luppold;C. Kittsteiner;H. Falk
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文献类型：
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作者：
Arno Luppold;C. Kittsteiner;H. Falk
为了缩短程序的执行时间，可以在编译时将其部分指令分配给快速ScratchPad存储器(SPM)。这是一种众所周知的技术，可用于最小化程序的最坏情况执行时间(WCET)。然而，现代嵌入式系统通常使用高速缓存的主存储器。SPM分配将不可避免地导致程序在主内存中的内存布局发生变化，从而改善或降低最坏情况下的缓存行为。我们通过提出一种基于整数线性规划的缓存感知SPM分配算法来解决这个问题，该算法考虑了最坏情况下缓存未命中行为的变化。
To improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.