Out-of-order vector architectures
Out-of-order vector architectures
复制标题
无序向量架构
DOI：
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发表时间：
1997
期刊：
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通讯作者：
James E. Smith
中科院分区：
文献类型：
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作者：
R. Espasa;M. Valero;James E. Smith
登记量重命名和置换指令问题现在已在超级处理器中常用。正如本文所示，这些技术也可以用于矢量处理器中的重要优势。性能得到改善，可用的内存带宽更有效。使用痕量驱动的仿真，我们根据凸C3400的传统矢量实现与drounder Out-Outs Outhor，Register，重命名，矢量实现进行了比较。当物理寄存器的数量高于12时，对于现实的内存延迟，置换式执行和寄存器重置的速度为1.24-1.72。排序技术还可以忍受100个周期的主存储潜伏期，其性能降解小于6％。用于寄存器重命名和排序问题的机制可用于支持精确的中断，从而在矢量机中是一个困难的问题。当实现精确的中断时，性能的降解通常小于10％。基于寄存器重命名的新技术针对动态消除溢出代码；该技术显示，该技术可提供1.10至1.20之间的额外速度，同时将总内存流量降低15-20％。
Register renaming and out-of-order instruction issue are now commonly used in superscalar processors. These techniques can also be used to significant advantage in vector processors, as this paper shows. Performance is improved and available memory bandwidth is used more effectively. Using a trace driven simulation we compare a conventional vector implementation, based on the Convex C3400, with an out-of-order, register renaming, vector implementation. When the number of physical registers is above 12, out-of-order execution coupled with register renaming provides a speedup of 1.24-1.72 for realistic memory latencies. Out-of-order techniques also tolerate main memory latencies of 100 cycles with a performance degradation less than 6%. The mechanisms used for register renaming and out-of-order issue can be used to support precise interrupts-generally a difficult problem in vector machines. When precise interrupts are implemented, there is typically less than a 10% degradation in performance. A new technique based on register renaming is targeted at dynamically eliminating spill code; this technique is shown to provide an extra speedup ranging between 1.10 and 1.20 while reducing total memory traffic by an average of 15-20%.