Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates
Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates
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DOI：
10.1088/1674-1056/21/10/108502
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发表时间：
2012-10
影响因子：
1.7
通讯作者：
Qiao Ming;Zhuang Xiang;Wu Lijuan;Zhang Wentong;Wen Hengjuan;Zhang Bo;L. Zhaoji
中科院分区：
文献类型：
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作者：
Qiao Ming;Zhuang Xiang;Wu Lijuan;Zhang Wentong;Wen Hengjuan;Zhang Bo;L. Zhaoji
基于对具有线性可变掺杂（LVD）的薄硅层（TSL）的理论和实验研究以及对具有多步场板（MSFP）的TSL LVD的进一步研究，本文提出了击穿电压（BV）模型并进行了实验验证。根据绝缘体上硅（SOI）器件的二维泊松方程，假设薄硅层漂移区的横向电场恒定。对于薄硅层中具有LVD的SOI器件，通过增强介电层场(ENDIF)研究BV对漏极下杂质浓度的依赖性，并由此推导出减小表面场(RESURF)条件。器件中心的漏极具有良好的自隔离效果，但高压互连（HVI）线的问题会变得严重。可以采用源场板和栅场板两级场板来屏蔽HVI对器件的不利影响。基于该模型，实现了带有MSFP的TSL LVD SOI n沟道横向双扩散MOSFET（nLDMOS）。 TSL LVD SOI器件的实验击穿电压（BV）和比导通电阻（Ron，sp）分别为694 V和21.3 Ω-mm2，漂移区长度为60 μm，埋氧层为3 μm，硅层为0.15 μm。
Based on the theoretical and experimental investigation of a thin silicon layer (TSL) with linear variable doping (LVD) and further research on the TSL LVD with a multiple step field plate (MSFP), a breakdown voltage (BV) model is proposed and experimentally verified in this paper. With the two-dimensional Poisson equation of the silicon on insulator (SOI) device, the lateral electric field in drift region of the thin silicon layer is assumed to be constant. For the SOI device with LVD in the thin silicon layer, the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field (ENDIF), from which the reduced surface field (RESURF) condition is deduced. The drain in the centre of the device has a good self-isolation effect, but the problem of the high voltage interconnection (HVI) line will become serious. The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device. Based on this model, the TSL LVD SOI n-channel lateral double-diffused MOSFET (nLDMOS) with MSFP is realized. The experimental breakdown voltage (BV) and specific on-resistance (Ron,sp) of the TSL LVD SOI device are 694 V and 21.3 Ω-mm2 with a drift region length of 60 μm, buried oxide layer of 3 μm, and silicon layer of 0.15 μm, respectively.