Register file design considerations in dynamically scheduled processors
Register file design considerations in dynamically scheduled processors
复制标题
动态调度处理器中的寄存器文件设计注意事项
DOI：
10.1109/hpca.1996.501172
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发表时间：
1996
期刊：
影响因子：
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通讯作者：
P. Chow
中科院分区：
文献类型：
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作者：
K. Farkas;N. Jouppi;P. Chow
我们已经使用寄存器重命名和调度队列进行了运行SPEC92基准的寄存器，研究了动态计划的处理器的寄存器文件要求。我们研究了能够每个周期发出四个或八个说明的处理器，发现在大多数情况下，实施精确例外的处理器需要相对较少的额外寄存器，而与不精确的例外相比。具有积极的非黑色负载支持的系统能够实现与带有完美内存系统的处理器相似的性能，而这些寄存器的成本为其他寄存器。鉴于我们的机器假设，我们发现具有32次派遣队列的四际机器的性能倾向于饱和80个寄存器。对于具有64个输入队列性能的八级机器，直到大约128个寄存器才能饱和。假设机器周期时间与寄存器文件周期时间成正比，则8号机器的性能仅比额外硬件的周期时间影响的4号机器的性能高20％。
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at processors capable of issuing either four or eight instructions per cycle and found that in most cases implementing precise exceptions requires a relatively small number of additional registers compared to imprecise exceptions. Systems with aggressive non-blacking load support were able to achieve performance similar to processors with perfect memory systems at the cost of some additional registers. Given our machine assumptions, we found that the performance of a four-issue machine with a 32-entry dispatch queue tends to saturate around 80 registers. For an eight-issue machine with a 64-entry dispatch queue performance does not saturate until about 128 registers. Assuming the machine cycle time is proportional to the register file cycle time, the 8-issue machine yields only 20% higher performance than the 4-issue machine due in part to the cycle time impact of additional hardware.