Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing
Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing
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基于 Razor 的可编程截断乘法和累加、节能以实现高效数字信号处理
DOI：
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发表时间：
2015
影响因子：
2.8
通讯作者：
R. Conway
中科院分区：
文献类型：
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作者：
M. D. L. G. Solaz;R. Conway
容错技术可以通过在精度和/或定时性能与功率之间进行权衡，来扩展通过动态电压调整实现的节能。这种能量改进强烈依赖于电路的延迟分布和输入信号的统计特性。独立地，可编程截断乘法器还以降低输出信噪比为代价来实现功率效益。在本文中，在容错数字信号处理(DSP)结构中使用了可编程截断乘法的组合，在该结构中，电源电压被降低到超过临界时序电平。对截断乘法的时序调制特性进行了分析和论证，以提高容错设计的性能，减少纠错负担，扩大系统的工作电压范围。将这两种电源策略结合使用可降低能耗水平，从而在将这两种技术与原始DSP相结合时实现超出预期的节能效果。
Fault tolerant techniques can extend the power savings achievable by dynamic voltage scaling by trading accuracy and/or timing performance against power. Such energy improvements have a strong dependency on the delay distribution of the circuit and the statistical characteristics of the input signal. Independently, programmable truncated multipliers also achieve power benefits at the expense of degradation of the output signal-to-noise ratio. In this brief, a combination of programmable truncated multiplication is used within a fault tolerant digital signal processing (DSP) structure in which the supply voltage is reduced beyond the critical timing level. Timing modulation properties of truncated multiplication are analyzed and demonstrated to improve the performance of fault tolerant designs, reducing error correction burdens, and extending the system operating voltage range. Combining both power strategies results in lower energy consumption levels, which improve the energy savings beyond that expected when applying a combination of both techniques with the original DSP.