A 4 $mu{ m W}/{ m Ch}$ Analog Front-End Module With Moderate Inversion and Power-Scalable Sampling Operation for 3-D Neural Microsystems
A 4 $mu{
m W}/{
m Ch}$ Analog Front-End Module With Moderate Inversion and Power-Scalable Sampling Operation for 3-D Neural Microsystems
复制标题
适用于 3D 神经微系统的 4 $mu{ m W}/{ m Ch}$ 模拟前端模块，具有适度反转和功率可扩展采样操作
DOI：
--
复制
发表时间：
2012
影响因子：
5.1
通讯作者：
E. Yoon
中科院分区：
文献类型：
--
作者：
K. Al;Sun;E. Yoon
本文报道了一个采用0.25 μ mCMOS工艺设计的用于三维神经记录微系统混合集成的模拟前端原型。为了实现大规模并行神经记录，原型研究了功率，面积，接口和模块化方面的一些关键电路挑战。我们实现了4 μW/通道的极低功耗，在低噪声放大器中使用适度反转优化了能效（K为5.98 ×108或NEF为2.9），并最大限度地减少了用于命令和数据捕获的异步接口（每16个通道仅2个）。我们还实现了自适应操作，包括可编程增益放大、功率可伸缩采样（高达50 kS/s/通道）、可编程增益和带宽的宽配置范围（9位）以及5位站点选择功能（从128个站点中选择16个站点）。实施的前端模块已经实现了减少噪声能量面积积的5-25倍的因素相比，国家的最先进的模拟前端的方法报告日期。
We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 ×108 or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.