A Low Power 128-pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks
A Low Power 128-pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks
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用于高性能无线个域网的 FFT/IFFT 低功耗 128 点实现
DOI：
10.1109/rme.2006.1689974
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
D. Pradhan
中科院分区：
文献类型：
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作者：
J. Mathew;K. Maharatna;D. Pradhan
提出了一种适用于IEEE 802.15.3a标准设计的低功耗128点FFT/IFFT处理器结构，将128点FFT分解为8点和16点FFT，再将16点FFT分解为4×4和2×8。分析表明，在面积适度增加的情况下，可以实现显着的功率降低。所提出的结构在312 ns内完成一次并行到并行(即当所有输入数据都并行可用且所有输出数据都并行产生)128点FFT计算。从算法和实现的角度分析了这些体系结构的优缺点。详细描述了块级结构的功耗分析。从功耗的角度来看，第二种架构更好；然而，与现有方案相比，这两种架构都显着降低了算法复杂度。对于第二种架构，核心功耗仅为72 mW。除了低功耗，该结构的优点还包括降低硬件复杂度、规则的数据流和简单的基于计数器的控制
An architecture for low power 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard design is proposed, where the 128-pt FFT is devolved into 8-pt and 16-pt FFTs and then once again by devolving the 16-pt FFT into 4times4 and 2times8. The analysis demonstrated that with modest increase in area one can achieve significant reduction in power. The proposed architectures complete one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 128-pt FFT computation in 312ns. The relative merits and demerits of these architectures have been analyzed from the algorithm as well as implementation point of view. Detailed power analysis of architecture at block level is described. From power perspective the second architecture is better; however both the architectures give significant reduction of algorithmic complexity compared to the existing schemes. For the second architecture the core power consumption is only 72mW. Apart from the low power consumption, the advantages of the proposed architecture include reduced hardware complexity, regular data flow and simple counter based control