Charge recovery implementation of an analog comparator: Initial results
Charge recovery implementation of an analog comparator: Initial results
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DOI：
10.1109/mwscas.2017.8053220
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发表时间：
2017-08
期刊：
影响因子：
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通讯作者：
Leo Filippini;L. Khuon;B. Taskin
中科院分区：
文献类型：
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作者：
Leo Filippini;L. Khuon;B. Taskin
介绍了一种适用于低功耗、低频应用的电荷恢复比较器电路。第一次，电荷恢复逻辑或绝热逻辑的原理被应用于模拟电路。比较器采用180 nm技术设计和仿真，并与最先进的解决方案进行比较。提取后的仿真结果表明，该比较器在标称PVT角处每次转换仅消耗46 fJ，总面积为45 μm2。所提出的比较器消耗高达70%的功率比最先进的动态锁存比较器。
This work introduces a charge recovery comparator circuit for low-power, low-frequency applications. For the first time, the principles of charge recovery logic, or adiabatic logic, are applied to an analog circuit. The comparator is designed and simulated in a 180 nm technology and compared to state of the art solutions. Post-extraction simulations show that the proposed comparator consumes only 46 fJ per conversion in the nominal PVT corner, while having a total area of 45 μm2. The proposed comparator consumes up to 70 % less power than a state of the art dynamic latch comparator.