A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS
A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS
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DOI：
10.1109/jssc.2012.2204543
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发表时间：
2012-07
影响因子：
5.4
通讯作者：
Tao Jiang;Wing Liu;Freeman Y. Zhong;Charlie Zhong;Kangmin Hu;P. Chiang
中科院分区：
文献类型：
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作者：
Tao Jiang;Wing Liu;Freeman Y. Zhong;Charlie Zhong;Kangmin Hu;P. Chiang
在40纳米CMOS工艺中制造了一种具有改进反馈延迟的单通道异步逐次逼近（SA）模数转换器（ADC）。与采用由数字反馈逻辑环路控制的单个量化器的传统逐次逼近寄存器（SAR）结构相比，所提出的SAR - ADC对每个转换位采用多个量化器，由每次量化后产生的异步纹波时钟驱动。因此，由于消除了数字逻辑延迟，6位ADC的采样率仅受电容数模转换器（Capacitive - DAC）建立的六个延迟以及每个比较器的量化延迟限制。40纳米CMOS SAR - ADC的测量结果在1 GS/s和1.25 GS/s时分别实现了32.9 dB和30.5 dB的峰值信噪失真比（SNDR），功耗为5.28 mW和6.08 mW，在小于170μm×85μm的核心面积内，其品质因数（FoM）分别为148 fJ/转换步和178 fJ/转换步。
A single-channel, asynchronous successive-approximation (SA) ADC with improved feedback delay is fabricated in 40 nm CMOS. Compared with a conventional SAR structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SAR-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparator's quantization delay, as the digital logic delay is eliminated. Measurement results of the 40 nm-CMOS SAR-ADC achieves a peak SNDR of 32.9 dB and 30.5 dB, at 1 GS/s and 1.25 GS/s, consuming 5.28 mW and 6.08 mW, leading to a FoM of 148 fJ/conv-step and 178 fJ/conv-step, respectively, in a core area less than 170 um by 85 um.