Instruction-level test methodology for CPU core self-testing
Instruction-level test methodology for CPU core self-testing
复制标题
CPU内核自测试的指令级测试方法
DOI：
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
Z. Navabi
中科院分区：
文献类型：
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作者：
S. Shamshiri;H. Esmaeilzadeh;Z. Navabi
TIS是一种用于处理器内核自测试的指令级方法，它通过测试指令增强了CPU的指令集。由于测试指令的功能与NOP指令相同，因此NOP指令可以用测试指令代替。在线测试可以在没有任何性能损失的情况下完成。TIS测试处理器的不同部分并检测固定故障。该方法可用于单周期、多周期和流水线处理器的离线和在线测试。但是，TIS更适合于在线测试的流水线结构，其中NOP指令频繁执行，因为数据，控制和结构的危险。运行测试指令而不是这些NOP指令，TIS利用了NOP浪费的时间。在这篇文章中，TIS的两种不同的实现。一种实现采用专用硬件模块来生成测试向量，而另一种实现是基于软件的方法，从内存中读取测试向量。这两种方法在流水线处理器核上实现，并比较了它们的面积开销。为了证明TIS测试技术的适当性，执行了几个程序，并给出了故障覆盖结果。
TIS is an instruction-level methodology for processor core self-testing that enhances instruction set of a CPU with test instructions. Since the functionality of test instructions is the same as the NOP instruction, NOP instructions can be replaced with test instructions. Online testing can be accomplished without any performance penalty. TIS tests different parts of the processor and detects stuck-at faults. This method can be employed in offline and online testing of single-cycle, multicycle and pipelined processors. But, TIS is more appropriate for online testing of pipelined architectures in which NOP instructions are frequently executed because of data, control and structural hazards. Running test instructions instead of these NOP instructions, TIS utilizes the time that is otherwise wasted by NOPs. In this article, two different implementations of TIS are presented. One implementation employs a dedicated hardware modules for test vector generation, while the other is a software-based approach that reads test vectors from memory. These two approaches are implemented on a pipelined processor core and their area overheads are compared. To demonstrate the appropriateness of the TIS test technique, several programs are executed and fault coverage results are presented.