Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time
Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time
复制标题
用于实现低于 100 ns 睡眠到活动模式转换时间的背栅偏置加速器
DOI：
10.1109/jssc.2008.2004528
复制
发表时间：
2008
影响因子：
5.4
通讯作者：
T. Sakurai
中科院分区：
文献类型：
--
作者：
D. Levacq;M. Takamiya;T. Sakurai
背栅偏置对于高速系统来说是一种很有前途的技术。通过反向偏压可以减少待机期间的泄漏，而活动模式下的足够偏压可以平衡工艺和温度变化。该技术在活动模式下不会带来延迟损失，但缓慢的唤醒时间会导致系统性能下降。在本文中，我们演示了一种通过直接连接到电源的大型 MOSFET 为背栅提供快速充电的电路。当背栅电压达到有源模式操作所需的偏置电压时，基于镜像延迟的电路用于精确关断该 MOSFET。尽管由于非线性背栅电容导致转换期间背栅充电速率不恒定，但仍实施非线性补偿操作以保证时序的精确控制。 90 nm CMOS 技术演示了大约 10 ns 的睡眠到活动模式转换。该加速器占据芯片总面积不到 2%，在转换期间消耗 600 muW，并且在活动和睡眠模式期间不添加任何偏置电流。
Backgate biasing is a promising technique for high speed systems. Leakage can be reduced during standby periods by reverse bias while adequate bias in active mode can balance process and temperature variations. This technique introduces no delay penalty in active mode but slow wake up time results in system performance degradation. In this paper, we demonstrate a circuit that provides fast charging of the backgate through a large MOSFET directly connected to the supply. A circuit based on a mirror delay is used to precisely turn off this MOSFET when the backgate voltage has reached the required bias voltage for active mode operation. A nonlinearity compensation operation is implemented to guarantee precise control of the timing despite a non-constant backgate charging rate during transition due to nonlinear backgate capacitance. A sleep-to-active mode transition on the order of 10 ns is demonstrated in a 90 nm CMOS technology. The accelerator occupies less than 2% of the total chip area, consumes 600 muW during the transitions and does not add any bias current during active and sleep modes.
用于片上电源电路的 VDD 跳变加速器可实现纳二阶瞬态时间
DOI：
--
发表时间：
2006
期刊：
IEEE Journal of Solid-State Circuits vol.41,no.11
影响因子：
--
作者：
Atsushi Kusunoki;Hideki Ohmagari;Takuya Yamamoto;Mitsuru T;S.Mikami;S.Mikami;H.Kawaguchi;K.Onizuka
通讯作者：
K.Onizuka