A 63 μg/√Hz Noise Floor and 14 pJ Power Efficiency Open-Loop MEMS Capacitive Accelerometer Using Closed-Loop Hybrid Dynamic Amplifier
A 63 μg/√Hz Noise Floor and 14 pJ Power Efficiency Open-Loop MEMS Capacitive Accelerometer Using Closed-Loop Hybrid Dynamic Amplifier
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DOI：
10.1109/tcsi.2023.3236369
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发表时间：
2023-01-18
影响因子：
5.1
通讯作者：
Zhu, Zhangming
中科院分区：
文献类型：
--
作者：
Zhong, Longjie;Liu, Shubin;Zhu, Zhangming
用于物联网（IoT）应用的MEMS电容式加速度计采用开环结构而不是闭环结构，以实现低功耗。在开环结构中，由于成本低，电压控制读出技术是首选。然而，电压控制读出技术存在噪声性能差和功率效率低（就FoM而言）的问题。本文提出了将闭环混合动态放大器与降噪技术相结合的弱反馈过采样逐次逼近读出电路，以达到低本底噪声、高功率效率和高精度的目的。所提出的基于WFB-OSA的读出电路采用商用0.18 μ m 1.8V CMOS工艺制造。测量结果表明，该电路的本底噪声为63 μ g/根Hz， FoM为14pJ。
MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than close-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, voltage control readout technique suffers from poor noise performance and low power efficiency (in terms of FoM). In this paper, the weak feedback oversampling successive approximation readout circuit which merges the closed-loop hybrid dynamic amplifier with noise reduction technique is proposed to achieve low noise floor, high power efficiency and high accuracy. The proposed WFB-OSA based readout circuit is fabricated in a commercial 0.18 mu m 1.8V CMOS process. The measurement result shows that the circuit has achieved a noise floor of 63 mu g/root Hz and an FoM of 14pJ.