Enabling system-level modeling of variation-induced faults in Networks-on-Chips
Enabling system-level modeling of variation-induced faults in Networks-on-Chips
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DOI：
10.1145/2024724.2024931
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发表时间：
2011-06
期刊：
影响因子：
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通讯作者：
Konstantinos Aisopos;C. Chen;L. Peh
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文献类型：
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作者：
Konstantinos Aisopos;C. Chen;L. Peh
工艺变异 (PV) 日益威胁着片上网络的可靠性。因此，最近提出并评估了各种弹性路由器设计。然而，这些评估假设随机故障分布，导致 52%–81% 的不准确度。我们提出了一种精确的电路级故障建模工具，该工具可以插入任何系统级 NoC 模拟器，量化运行时 PV 引起的故障的系统级影响，查明应保护的容易出现故障的路由器组件，并准确评估替代的弹性多核设计。
Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%–81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs.