Analysis of data dependence of leakage current in CMOS cryptographic hardware
Analysis of data dependence of leakage current in CMOS cryptographic hardware
复制标题
CMOS密码硬件中漏电流的数据依赖性分析
DOI：
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发表时间：
2007
期刊：
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通讯作者：
A. Trifiletti
中科院分区：
文献类型：
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作者：
J. Giorgetti;G. Scotti;A. Simonetti;A. Trifiletti
提出了一种基于泄漏功耗测量的CMOS密码硬件功耗分析方法。本文综述了预测CMOS门极最大和最小漏电流输入矢量的算法和模型。广泛的晶体管级模拟一个简单的CMOS密码核心。本文报道了在0.13 μ mCMOS工艺中实现的用于密码学应用的ASIC上进行的漏电流测量。这项工作的结果表明，泄漏电流可以利用作为侧通道的攻击者提取信息的密钥在短通道CMOS技术实现的密码硬件。
A novel power analysis technique for CMOS cryptographic hardware based on leakage power consumption measurements is presented. Algorithms and models to predict the input vector for maximum and minimum leakage currentallin CMOS gates are reviewed. Extensive transistor level simulations on a simple CMOS crypto core are presented. Leakage current measurements carried out on an ASIC for cryptographic applications implemented in a 0.13 um CMOS technology are reported. The results of this work show that leakage current can be exploited as a side channel by an attacker to extract information about the secret key in cryptographic hardware implemented in short channel CMOS technologies.