Code placement for improving dynamic branch prediction accuracy
Code placement for improving dynamic branch prediction accuracy
复制标题
用于提高动态分支预测准确性的代码放置
DOI：
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
Daniel A. Jiménez
中科院分区：
文献类型：
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作者：
Daniel A. Jiménez
传统上，代码放置技术通过增加指令局部性和减少采用的分支的数量来提高指令提取带宽。然而，传统的代码放置技术在存在改变指令高速缓存中的指令的放置的跟踪高速缓存的情况下具有较少的益处。此外，随着管线变得更深以适应增加的时钟速率，分支误预测惩罚已成为性能的显著障碍。我们评估模式历史表分区，反馈指导的代码放置技术，明确地放置条件分支，使它们不太可能相互干扰破坏性的分支预测表。在英特尔奔腾4上运行的SPEC CPU基准测试中，分支预测错误平均减少了22%和3.5%。这种减少产生了高达16.0%和4.5%的平均加速。相比之下，分支对齐，一种以前的代码放置技术，只能产生高达4.7%的加速比，平均不到1%。
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditional code placement techniques have less benefit in the presence of a trace cache that alters the placement of instructions in the instruction cache. Moreover, as pipelines have become deeper to accommodate increasing clock rates, branch misprediction penalties have become a significant impediment to performance. We evaluate pattern history table partitioning, a feedback directed code placement technique that explicitly places conditional branches so that they are less likely to interfere destructively with one another in branch prediction tables. On SPEC CPU benchmarks running on an Intel Pentium 4, branch mispredictions are reduced by up to 22% and 3.5% on average. This reduction yields a speedup of up to 16.0% and 4.5% on average. By contrast, branch alignment, a previous code placement technique, yields only up to a 4.7% speedup and less than 1% on average.