Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time $DeltaSigma$ Modulators
Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time $DeltaSigma$ Modulators
复制标题
补偿连续时间 $DeltaSigma$ 调制器中超过一个时钟周期的量化器延迟
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
S. Pavan
中科院分区：
文献类型：
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作者：
Vikas Singh;N. Krishnapura;S. Pavan
连续时间ΔΣ调制器的最大采样速率受到量化器延迟的限制。大多数常规延迟补偿技术解决小于一个时钟周期的延迟。先前提出的用于补偿带通调制器中超过时钟周期的量化器延迟的技术涉及绕过量化器的并行反馈路径。我们分析了这种技术的低通调制器，并表明，采样率迄今不可能实现。设计权衡的影响，并给出仿真结果表明该技术的有效性。
The maximum sampling rate of a continuous-time ΔΣ modulator is limited by quantizer delay. Most conventional delay compensation techniques address less than a clock cycle of delay. A technique previously proposed for compensating quantizer delays in excess of a clock cycle in bandpass modulators involves a parallel feedback path that bypasses the quantizer. We analyze this technique for low-pass modulators and show that sampling rates hitherto not possible can be achieved. Design tradeoffs are investigated, and simulation results showing the effectiveness of the technique are given.