The Beetle Reference Manual - chip version 1.3, 1.4 and 1.5
The Beetle Reference Manual - chip version 1.3, 1.4 and 1.5
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Beetle 参考手册 - 芯片版本 1.3、1.4 和 1.5
DOI：
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发表时间：
2006
期刊：
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通讯作者：
M. Schmelling
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文献类型：
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作者：
S. Löchner;M. Schmelling
本文详细介绍了读出芯片Beetle1.3、1.4和1.5的电气规格、工作条件和端口定义。该芯片是为LHCb实验开发的，满足多阳极光电倍增管读出时硅顶点检测器（VELO、VETO）、硅跟踪器和RICH检测器的要求。它集成了128个通道与低噪声电荷敏感前置放大器和整形器。脉冲形状可以选择，使其符合LHCb规范：峰值时间为25ns， 25ns后峰值电压的余量小于30%。具有可配置极性的每个通道的比较器提供二进制信号。四个相邻的比较器通道通过LVDS端口被输入并带出芯片。整形器或比较器输出以40 MHz的lhcluster交叉频率采样到模拟管道中。这个环形缓冲器具有最大的可编程延迟。160个采样间隔和一个集成的16级非随机缓冲。对于模拟读出数据多路复用高达40MHz到1或4个端口。二进制读出模式在两个端口上以高达80MHz的输出速率工作。当前驱动程序将序列化的数据带离芯片。该芯片可以接受高达1.1 MHz的触发率，每个触发器在900 ns内执行无死时间读出。为了可测试性和校准目的，实现了脉冲高度可调的电荷注入器。偏置设置和各种其他参数可以通过一个标准的ic接口来控制。已采取适当的设计措施，以确保对总电离剂量效应的辐射硬度不超过10mrad。通过冗余逻辑实现了对单事件扰动的鲁棒性。∗电子邮件:loechner@kip.uni-heidelberg.de
This paper details the electrical specifications, operating conditions and port definitions of the readout chip Beetle1.3, 1.4 and 1.5. The chip is developed for the LHCb experiment and fulfils the requirements of the silicon vertex detector (VELO, VETO), the silicon tracker and the RICH detector in case of multi-anode photomultiplier readout. It integrates 128 channels with low-noise charge-sensitive preamplifiers and shapers. The pulse shape can be chosen such that it complies with LHCb specifications: a peaking time of 25 ns with a remainder of the peak voltage after 25 ns of less than 30%. A comparator per channel with configurable polarity provides a binary signal. Four adjacent comparator channels are being ORed and brought off chip via LVDS ports. Either the shaper or comparator output is sampled with the LHCbunch-crossing frequency of 40 MHz into an analog pipeline. This ring buffer has a programmable latency of max. 160 sampling intervals and an integrated derandomising buffer of 16 stages. For analog readout data is multiplexed with up to 40MHz onto 1 or 4 ports. A binary readout mode operates at up to 80MHz output rate on two ports. Current drivers bring the serialised data off chip. The chip can accept trigger rates of up to 1.1 MHz to perform a dead-timeless readout within 900 ns per trigger. For testability and calibration purposes, a charge injector with adjustable pulse height is implemented. The bias settings and various other parameters can be controlled via a standard IC-interface. Appropriate design measures have been taken to ensure the radiation hardness against total ionising dose effects in excess of 10 Mrad. A robustness against Single Event Upset is achieved by redundant logic. ∗Email: loechner@kip.uni-heidelberg.de