Analysis of Placement Procedures for VLSI Standard Cell Layout
Analysis of Placement Procedures for VLSI Standard Cell Layout
复制标题
VLSI标准单元布局的贴装程序分析
DOI：
10.1145/318013.318062
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发表时间：
1986
期刊：
影响因子：
--
通讯作者：
M. Hartoog
中科院分区：
文献类型：
--
作者：
M. Hartoog
本文对VLSI标准单元布局的布局过程进行了研究。所研究的程序包括模拟退火法、Min Cut布局，以及对Min Cut布局的一些改进，包括一种名为终端传播的技术，该技术允许Min Cut包括与外部单元连接的影响。Min Cut程序与力定向成对交换(FDPI)算法相结合，以改进布局。对于相同的问题，这些技术产生了一系列解决方案，典型的标准偏差为总导线长度的4%和布线区域的3%至4%。模拟退火法的计算结果分布范围更大。给定算法的结果的这种分布意味着在比较算法时应该使用许多布局的平均结果。我们发现，简化终端传播的最小割划分是所研究的最有效的布局方法。
This paper describes a study of placement procedures for VLSI Standard Cell Layout. The procedures studied are Simulated Annealing, Min Cut placement, and a number of improvements to Min Cut placement including a technique called Terminal Propagation which allows Min Cut to include the effect of connections to external cells. The Min Cut procedures are coupled with a Force Directed Pairwise Interchange (FDPI) algorithm for placement improvement. For the same problem these techniques produce a range of solutions with a typical standard deviation 4% for the total wire length and 3% to 4% for the routed area. The spread of results for Simulated Annealing is even larger. This distribution of results for a given algorithm implies that mean results of many placements should be used when comparing algorithms. We find that the Min Cut partitioning with simplied Terminal Propagation is the most efficient placement procedure studied.