Selective electroless copper for VLSI interconnection
Selective electroless copper for VLSI interconnection
复制标题
用于 VLSI 互连的选择性化学镀铜
DOI：
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发表时间：
1989
影响因子：
4.9
通讯作者：
C. Ting
中科院分区：
文献类型：
--
作者：
P. Pai;C. Ting
铜被研究作为低电阻VLSI互连的候选者。仿真研究表明，当有效沟道长度小于0.5 μ m时，互连线的RC时间常数是总延迟的主要部分。通过降低互连线的电阻率，可以在不改变设计规则的情况下将操作速度提高20%以上。采用选择性化学沉积工艺解决了铜图案化的难题。用这种方法已经实现了2.2 μ m间距的图案。铜污染的问题也进行了研究，介电膜，如氮氧化硅和氮化硅被证明是有效的，在停止铜扩散。在铜表面镀一层镍膜，可使铜在100 ℃、4%KCl溶液中的腐蚀速度从0.2 μ m/h降低到0.05 μ m/h以下。<<ETX>>
Cu is studied as a candidate for low-resistance VLSI interconnection. Simulation studies show that for effective channel length less than 0.5 mu m, the RC time constant of interconnection is a major part of the total delay. By reducing the resistivity of the interconnect, the operating speed can be increased by more than 20% without any change in design rule. A selective electroless deposition process was used to solve the Cu patterning difficulty. Patterns of 2.2- mu m pitch have been achieved with this process. The copper contamination issue is also studied; dielectric films such as silicon oxynitride and silicon nitride are shown to be effective in stopping Cu diffusion. By coating a thin Ni film on Cu, Cu corrosion can be reduced from 0.2 mu /h to less than 0.05 mu m/h at 100 degrees C in 4% KCL solution.<<ETX>>