A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
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DOI：
10.1109/tcsi.2012.2230506
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发表时间：
2013-03
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影响因子：
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通讯作者：
Chiu-Wing Sham;Xu Chen;F. Lau;Yue Zhao;W. Tam
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文献类型：
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作者：
Chiu-Wing Sham;Xu Chen;F. Lau;Yue Zhao;W. Tam
本文提出了一种低密度奇偶校验卷积码（LDPCCC）的解码器结构。具体地，LDPCCC从准循环（QC）LDPC块码导出。通过利用准循环结构，建议LDPCCC解码器采用了动态的消息存储在存储器中，并使用一个简单的地址控制器。解码器有效地将流水线处理器中的存储器组合成一个大的存储器块，以便利用现代现场可编程门阵列（FPGA）中嵌入式存储器的数据宽度。在Altera Stratix FPGA上实现了5/6速率的QC-LDPCCC。它的吞吐量高达2.0 Gb/s，时钟频率为100 MHz。此外，解码器显示出低于10-13的比特能量噪声功率谱密度比（Eb/N 0）为3.55 dB的优良的错误性能。
This paper proposes a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10-13 at a bit-energy-to-noise power-spectral-density ratio (Eb/N0) of 3.55 dB.