Core network interface architecture and latency constrained on-chip communication
Core network interface architecture and latency constrained on-chip communication
复制标题
核心网络接口架构和延迟受限的片上通信
DOI：
10.1109/isqed.2006.41
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
R. Mahapatra
中科院分区：
文献类型：
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作者：
Praveen Bhojwani;R. Mahapatra
提出了一种用于IP核与片上网络接口的核心网络接口（CNI）结构。除了分组通信请求和响应的基本功能之外，我们期望CNI提供对复杂片上系统（SoC）中的通信至关重要的附加服务。一个CNI接口与OCP兼容的核心接口的架构验证。在改进的片上路由器的支持下，CNI被设置为约束片上通信延迟抖动。我们观察到，由于在片上互连网络的特定配置中低效的虚拟通道分配导致的抖动导致高达400%的延迟变化。在2D环面网络中使用基于类的虚拟信道分配方案，我们提供可预测的端到端延迟。虽然所提出的方案不能保证最小可能的端到端延迟，但它提供了受约束的边界
This paper proposes a core network interface (CNI) architecture to interface IP cores with on-chip networks. Besides the basic functionality of packetizing communication requests and responses, we expect the CNI to provide additional services critical to communication in complex systems-on-a-chip (SoC). A CNI for interfacing with OCP-compliant core interfaces was developed for architecture validation. With the support of a modified on-chip router, the CNI was setup to bound on-chip communication latency jitter. We observed that jitter due to inefficient virtual channel allocation in a particular configuration of an on-chip interconnection network lead to latency variations of up to 400%. Using a class-based virtual channel allocation scheme in a 2D torus network, we provide for predictable end-to-end latency. While the proposed scheme does not guarantee least possible end-to-end latency, it provides for constrained bounds