Ultra low-cost defect protection for microprocessor pipelines
Ultra low-cost defect protection for microprocessor pipelines
复制标题
微处理器管道的超低成本缺陷保护
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
T. Austin
中科院分区：
文献类型：
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作者：
S. Shyam;Kypros Constantinides;Sujay Phadke;V. Bertacco;T. Austin
随着技术尺寸越来越小，器件的可靠性已成为下一代设计关注的首要问题。晶体管磨损和制造缺陷等硅失效机制是一个日益严峻的挑战，威胁着未来系统的产量和产品寿命。在本文中，我们介绍了 BulletProof 管道，这是第一个保护微处理器管道和片上存储系统免受硅缺陷影响的超低成本机制。为了实现这一目标，我们将节省面积的在线测试技术和系统级检查点相结合，以提供与传统解决方案相同的可靠性保证，但成本却低得多。我们的方法利用微架构检查点机制，该机制创建粗粒度的执行时期，在此期间分布式在线内置自测试（BIST）机制验证底层硬件的完整性。一旦检测到故障，我们依靠指令级并行处理器的自然冗余来修复系统，使其仍然可以在性能下降的模式下运行。使用详细的电路级和架构模拟，我们发现我们的方法以很少的面积成本（5.8％）提供了非常高的硅缺陷覆盖率（89％）。此外，当出现缺陷时，随后的降级操作模式被发现仅对性能产生中等影响（从 4% 降低到 18%）。
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal we combine area-frugal on-line testing techniques and system-level checkpointing to provide the same guarantees of reliability found in traditional solutions, but at much lower cost. Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity of the underlying hardware. In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode. Using detailed circuit-level and architectural simulation, we find that our approach provides very high coverage of silicon defects (89%) with little area cost (5.8%). In addition, when a defect occurs, the subsequent degraded mode of operation was found to have only moderate performance impacts, (from 4% to 18% slowdown).