Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design
Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design
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客座编辑简介：纳米 CMOS 设计的可靠性挑战
作者：
Yu Cao;J. Tschanz;P. Bose
超大规模集成电路设计是由一个不断增加的挑战，以科普不可靠的组件在设备，电路和系统的水平。可靠性挑战包括，例如，偏置温度不稳定性（BTI），介电击穿，早期寿命故障和软错误，以及它们与统计过程变化的相互作用。不可靠性的影响必须在设计抽象的各个层次进行管理。这个特殊的问题解决了在32纳米节点和超越的可靠性设计的问题，在VLSI芯片设计中使用的逐渐不可靠的组件的新兴威胁的背景下。
VLSI design is driven by an ever-increasing challenge to cope with unreliable components at the device, circuit, and system levels. Reliability challenges include, for example, bias-temperature instability (BTI), dielectric breakdown, early-life failure, and soft errors, as well as their interaction with statistical process variation. The impact of unreliability must be managed at various levels of the design abstraction. This special issue addresses the problem of design for reliability at the 32-nm node and beyond, in the context of the emerging threat of progressively unreliable components used in VLSI chip design.