An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies
An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies
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CNTFET 和 QCA 技术中二元伽罗瓦域的并发错误检测研究
DOI：
10.1109/isvlsi.2012.57
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发表时间：
2012
期刊：
影响因子：
--
通讯作者：
S. Mohanty
中科院分区：
文献类型：
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作者：
Mahesh Poolakkaparambil;J. Mathew;A. Jabir;S. Mohanty
永久性和暂时性暂态故障是现代超大规模集成电路（VLSI）中主要关注的问题。现代集成电路具有如此高的易损性，其主要原因是其高集成密度。器件的小型化导致其性能随尺寸而缩放，从而使其成为诱发故障和永久故障的对象。随着研究的进展，该技术甚至进一步缩小到15nm或以下，潜在的CMOS替代策略，如碳纳米管场效应晶体管（CNTFET）和量子细胞自动机（QCA）细胞，故障敏感性的概念进一步增加。鉴于此，本文以正态基有限场乘法器电路为试验台，研究了标准并发错误检测（CED）方案在cntefet和QCA技术上的性能。然后将结果与他们的CMOS等效物进行比较，这被认为是作者所知的第一次报道的尝试。对采用CNTFET设计的CMOS进行了详细的实验分析，证明了与等效CMOS相比，新兴技术在面积、功耗和延迟方面具有更好的容错设计。
Permanent and temporary transient faults are the main concern in modern very large scale integrated circuits (VLSI). The main reason for such high vulnerability of the modern integrated circuit is their high integration density. Miniaturization of devices resulted in scaling their properties along with their size and thus making them a subject to induced faults and permanent faults. As the research progresses towards shrinking the technology even further to 15nm or below with potential CMOS replacement strategies such as carbon nano-tube field effect transistors (CNTFET) and quantum cellular automata (QCA) cells, the notion of fault susceptibility increases even further. Owing to these facts, this paper investigates the performance of standard concurrent error detection (CED) scheme over CNTEFETs and QCA technologies using normal basis (NB) finite field multiplier circuit as a test bench. The results are then compared with their CMOS equivalents which are believed to be the first reported attempt to the best of the authors'knowledge. The detailed experimental analysis of CMOS with CNTFET design proves that the emerging technologies perform better for error tolerant designs in terms of area, power, and delay as compared to its CMOS equivalent.