A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems
复制标题
具有稀疏和可重构自旋互连的可扩展 CMOS Ising 计算机，用于解决组合优化问题
DOI：
10.1109/jssc.2022.3142896
复制
发表时间：
2022
影响因子：
5.4
通讯作者：
Bongjin Kim
中科院分区：
文献类型：
--
作者：
Yuqi Su;Junjie Mu;Hyunjoon Kim;Bongjin Kim
现有的算法都无法找到被归类为非确定性多项式时间（NP）难题的组合优化问题（COP）的精确解。另外，基于伊辛模型和退火过程的伊辛计算机最近引起了极大关注。伊辛计算机可以通过观察动态自旋态的收敛来找到NP难的COP的近似解。然而，它们在将优化问题映射到具有固定自旋互连的不灵活的伊辛计算机上遇到了挑战。在本文中，我们提出了一种具有稀疏且可重构自旋互连的可扩展CMOS伊辛计算机，用于以最小的开销对自旋网络进行任意映射。在没有映射算法的情况下，所提出的伊辛计算机提供了一种将COP直接映射到可重构硬件的方法。我们制造了一个具有252个自旋的65纳米CMOS伊辛测试芯片，并用于解决包括最大割问题在内的COP。
No existing algorithms can find exact solutions to the combinatorial optimization problems (COPs) classified as non-deterministic polynomial-time (NP) hard problems. Alternatively, Ising computer based on the Ising model and annealing process has recently drawn significant attention. The Ising computers can find approximate solutions to the NP-hard COPs by observing the convergence of dynamic spin states. However, they have encountered challenges in mapping the optimization problems to the inflexible Ising computers with fixed spin interconnects. In this article, we propose a scalable CMOS Ising computer with sparse and reconfigurable spin interconnects for arbitrary mapping of spin networks with minimal overhead. Without a mapping algorithm, the proposed Ising computer provides a method for directly mapping COPs to the reconfigurable hardware. A 65-nm CMOS Ising test chip with 252 spins is fabricated and used for solving COPs, including max-cut problems.