Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
复制标题
65 nm 10T 亚阈值 SRAM 中中子引起的软错误和多单元翻转
DOI：
10.1109/tns.2011.2159993
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发表时间：
2011
影响因子：
1.8
通讯作者：
T. Onoye
中科院分区：
文献类型：
--
作者：
H. Fuketa;M. Hashimoto;Y. Mitsuyama;T. Onoye
本文在分析了现有文献的基础上，在1.0 ~ 0.3V电源电压范围内，测量了65 nm 10 T静态随机存储器（SRAM）中中子引起的软错误率（SER）。结果表明，在0.3V电源电压下，中子引起的SER约为1.0V电源电压下的8倍。对电源电压和井间距离的影响也进行了研究。MCU速率对1.0 V和0.5 V之间的电源电压的依赖性很小，并且随着电压降低到0.5 V以下而增加。这是因为另一种机制（例如电荷共享）的影响在亚阈值区域变得更大，而不是寄生双极效应，寄生双极效应被认为是导致SRAM中MCU在我们的设计中处于标称电源电压的主要机制。
In this paper, the soft error rate (SER) induced by neutrons in 65-nm 10T static random access memory (SRAM) is measured over a wide range of supply voltages from 1.0 to 0.3 V. The results show that the neutron-induced SER at 0.3 V is around eight times that at 1.0 V. The dependence of multiple cell upsets (MCUs) on the supply voltage and on the distance between well ties is also investigated. The dependence of the MCU rate on the supply voltage between 1.0 and 0.5 V is small and increases as the voltage is reduced below 0.5 V. This is because the effect of another mechanism, such as charge-sharing, becomes larger in the subthreshold region, rather than the parasitic bipolar effect, which is considered the dominant mechanism causing MCUs in SRAM at the nominal supply voltage in our design.